TMS320VC5502PGF300

fixed-point digital signal processor, 4.5 V, QFP

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Price:: US $7.89~8.15 / piece [Get Latest Price]

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PartNumber:: TMS320VC5502PGF300

Brand:: Texas Instruments - TI | Pack: QFP | D/C: 10+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2012-08-28

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Part Number:TMS320VC5502PGF300
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Product Summary

The TMS320VC5502PGF300 is a fixed-point digital signal processor (DSP) is based on the TMS320C55x. DSP generation CPU processor core. The TMS320VC5502PGF300 DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The TMS320VC5502PGF300 supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform data transfers independent of the CPU activity. The TMS320VC5502PGF300 provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the TMS320VC5502PGF300 CPU.

Parametrics

TMS320VC5502PGF300 absolute maximum ratings: (1)Supply voltage I/O range, DVDD: －0.3 V to 4.0 V; (2)Supply voltage core range, CVDD: －0.3 V to 2.0 V; (3)Input voltage range, VI: －0.3 V to 4.5 V; (4)Output voltage range, Vo: －0.3 V to 4.5 V; (5)Operating case temperature range, TC: －40°C to 85°C; (6)Storage temperature range, Tstg: －55°C to 150°C.

Features

TMS320VC5502PGF300 features: (1) 8M ×16-Bit Maximum Addressable External; (2)Memory Space; (3) 16K ×16-Bit One-Wait-State On-Chip ROM (32K Bytes); (4) Instruction Cache (16K Bytes); (5) On-Chip Scan-Based Emulation Logic; (6) IEEE Std 1149.1(1) (JTAG) Boundary Scan Logic; (7) Programmable Low-Power Control of Six Device Functional Domains.